Invention relates to a semiconductor device comprising a dual-gate insulated gate field effect device such as a MOS tetrode.
Such devices are particularly suitable for use as amplifier elements in high frequency pre-amplifiers of, for example, radio or television receivers in which a signal received by an antenna of the receiver is applied to one insulated gate of the insulated gate field effect device and the other insulated gate is connected to a voltage supply which can be adjusted to control the gain of the insulated gate field effect device so that the amplified signals have a substantially constant amplitude, regardless of the amplitude of the input signal.
In order to provide the insulated gate field effect device with the required high transconductance, the conduction channel of the device should be large in a direction transverse to the path of charge carriers through the conduction channel. Conventionally, this "transverse" direction is referred to as the channel width while the parallel direction is referred to as the channel length. In addition to a large width, a short conduction channel length is desired to give a high transconductance and low gate-source capacitance.
EP-A-76006 describes an example of such an insulated gate field effect device having a source region surrounding its drain region to define therebetween a conduction channel shaped so that the two insulated gates which overlie the conduction channel follow a meandering path with a first one of the insulated gates surrounding the drain region and the second one of the insulated gates surrounding the first insulated gate. As shown in EP-A-76006, a break or interruption is provided in the outer insulated gate in the vicinity of the connection between the inner insulated gate and its bond pad. The two ends of the outer insulated gate are extended and connected to a single bond pad. This arrangement allows the bond pads to be positioned on the surrounding insulating region well away from the active device area, so reducing parasitic capacitance effects.
The conductive layers of the insulated gates of the device described in EP-A-76006 are formed of aluminum. Aluminum is highly conductive and so the frequency response of the device is not unduly affected by the provision of the long narrow strips of aluminum required to provide the necessary wide yet short conduction channel regions. Typically, the width of the conduction channel region may be 750 to 1000 times its length.
The use of a self-aligned technology in which the source and drain regions are formed using the insulated gates as a mask is desirable because it enables shorter channel lengths and smaller gate to source/drain overlaps and thus smaller parasitic capacitances. However, aluminum is not suitable for use in a self-aligned technology because the aluminum conductive layers of the insulated gates cannot be subjected to the high temperature processes used to the form the source and drain regions.
Materials suitable for forming the conductive layers of insulated gates which can withstand such high temperature processing include doped polycrystalline silicon and refractory metal silicides such as titanium or cobalt silicide. The materials which can be used in a self-aligned technology have a much higher resistance than aluminum and so simply replacing the aluminum gate with a gate made of such a material would result in a device having a high gate resistance which may cause an unacceptably large attenuation of the input signal or a correspondingly high noise figure at high frequencies, resulting in a significant limitation in the frequency response of the device. Accordingly if a self-aligned technology is to be used, alternative geometries have to be adopted. A paper entitled "a UHF MOS Tetrode with polysilicon gate" by F. M. Klaassen et. al. published in Solid State Electronics Volume 23, 1980 at pages 23 to 30 describes a MOS tetrode in which an interdigitated comb-like structure is adopted for the insulated gates with each insulated gate being divided into a number of fingers (the teeth of the comb) which are connected, away from the active device area, by a high conductivity insulated gate conductor made of, for example, aluminum or an aluminium alloy. The overall gate width of each insulated gate is thus divided into a series of insulated gate sections or fingers connected in parallel by a highly conductive insulated gate conductor, so reducing the overall gate resistance.
Each insulated gate section of this structure has to extend beyond the active device area onto the surrounding insulating region both to enable connection to the respective one of the insulated gate conductors and to provide a well-defined edge to the insulated gate structure. In order to achieve a desirably low output capacitance, the semiconductor body should have a body region with a very low doping, typically 0.7.times.10.sup.15 to 1.times.10.sup.15 atom cm.sup.-2, at least adjacent the one major surface. Thermal oxide such as gate oxide typically has 1.times.10.sup.11 to 2.times.10.sup.11 positive charges per cm.sup.2 within about 5 nm of a silicon-silicon oxide interface and accordingly such a lowly doped body region can be expected to be inverted and so to form a conduction channel with as little as 10.sup.9 to 10.sup.11 electrons cm.sup.-2 under insulating material thicker than 50 nm. Accordingly, there is a problem with leakage currents where the ends of the insulated gates extend onto the surrounding insulating region. This problem is considerably greater in a self-aligned technology device, which may have, for example, twenty insulated gate sections, than in an aluminum gate technology.
Special steps need to be taken to reduce leakage current at the ends of the insulated gates. One method of reducing this leakage current is to ensure that there is a distance of 2-3 micrometers (.mu.m) of the lowly doped body region over which the ends of the insulated gate sections pass before extending onto the surrounding insulating region. Once allowance has been made for alignment tolerances there is about 6 .mu.m at each end of each insulated gate section which can carry no current but which does add to the parasitic capacitance problem and which, for a self-aligned technology device with many parallel-connected insulated gate sections, can represent about a 20% (percent) increase in the gate capacitance.